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<p class="MsoPlainText">Dear HPC users,<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">we would like to draw your attention on the following PRACE Advanced Training Centre (PATC) events @ LRZ, Germany in April/May 2017:<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoNormal"><b>PRACE PATC Course: Advanced Topics in High Performance Computing
<o:p></o:p></b></p>
<p class="MsoNormal"><span style="color:#1F497D"><a href="https://events.prace-ri.eu/event/535/">https://events.prace-ri.eu/event/535/</a><o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b>Date:</b> Monday, April 3, 2017 - Thursday, April 6, 2017, 9:00-18:00<o:p></o:p></p>
<p class="MsoNormal"><b>Registration deadline:</b> March 20, 2017<o:p></o:p></p>
<p class="MsoNormal"><b><span lang="DE">Lecturers:</span></b><span lang="DE"> Dr. R. Bader, Dr. S. Mendez, Dr. V. Weinberg (LRZ), Dr.-Ing.
</span>J. Eitzinger, Dr. M. Wittmann (RRZE)<o:p></o:p></p>
<p class="MsoNormal"><b>Topics:</b> Processor-specific optimisation, Parallel I/O with MPI I/O, tuning of I/O on LRZ's HPC systems, I/O libraries, Intel Xeon Phi programming, PGAS programming<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b>NEW Workshop @ LRZ:<o:p></o:p></b></p>
<p class="MsoNormal"><b>PRACE PATC Course: HPC code optimisation workshop <o:p></o:p></b></p>
<p class="MsoNormal"><span style="color:#1F497D"><a href="https://events.prace-ri.eu/event/607/">https://events.prace-ri.eu/event/607/</a>
</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:black"><o:p> </o:p></span></p>
<p class="MsoPlainText"><b>Date:</b> Thursday, May 4, 2017, 9:00-17:00 <o:p></o:p></p>
<p class="MsoPlainText"><b>Registration deadline:</b> April 20, 2017<o:p></o:p></p>
<p class="MsoPlainText"><b>Lecturers:</b> Dr. Fabio Baruffa, Dr. Luigi Iapichino (Intel Parallel Computing Centre @ LRZ)<o:p></o:p></p>
<p class="MsoPlainText"><b>Abstract:</b> The workshop is organised as a compact course on techniques and methods, focused on code improvement and exploration of the latest Intel processor features, in particular the vector units. During this optimisation process,
the attendees will learn how to enable vectorisation using simple pragmas and more effective techniques, like changing data layout and alignment. This work is guided by the hints from the Intel compiler reports, and using Intel Advisor. The outline of the
workshop includes: basics on modern computer architectures, optimisation process and vectorisation, Intel Advisor. We provide also an N-body code, to support the described optimisation solutions with practical examples.<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText">Please also pass this course announcement to other interested colleagues.
<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText">Information on further HPC courses:<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"> - by LRZ: <a href="http://www.lrz.de/services/compute/courses/">http://www.lrz.de/services/compute/courses/</a><o:p></o:p></p>
<p class="MsoPlainText"> - by the Gauss Centre of Supercomputing (GCS): <a href="http://www.gauss-centre.eu/training">http://www.gauss-centre.eu/training</a><o:p></o:p></p>
<p class="MsoPlainText"> - by the PRACE Advanced Training Centres (PATCs): <a href="http://www.training.prace-ri.eu/">
http://www.training.prace-ri.eu/</a><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><span lang="DE">Kind regards,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="DE">Volker Weinberg<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="DE"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="DE">--<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="DE">Dr. Volker Weinberg <o:p>
</o:p></span></p>
<p class="MsoPlainText"><span lang="DE">Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften<o:p></o:p></span></p>
<p class="MsoPlainText">- High Performance Computing Group -<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">email: <a href="mailto:weinberg@lrz.de">weinberg@lrz.de</a><o:p></o:p></p>
<p class="MsoPlainText">address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
<o:p></o:p></p>
<p class="MsoPlainText">room: E.1.016<o:p></o:p></p>
<p class="MsoPlainText">phone: +49 (89) 35831-8863 <o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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