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<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Dear HPC<span style="color:black"> users</span>,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Interested in optimising your parallel code? Then join our new one-day PRACE “HPC Code Optimisation Workshop” in May at Leibniz Supercomputing Centre, Germany.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Two leading experts from our Intel Parallel Computing Centre will share their know-how in code optimisation.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span lang="EN-GB">NEW PRACE Workshop @ LRZ: <span style="color:black">
<o:p></o:p></span></span></b></p>
<p class="MsoNormal"><b><span lang="EN-GB">HPC <span style="color:black">C</span>ode
<span style="color:black">O</span>ptimisation <span style="color:black">W</span>orkshop
<o:p></o:p></span></b></p>
<p class="MsoNormal"><span lang="EN-GB" style="color:#1F497D"><a href="https://events.prace-ri.eu/event/607/">https://events.prace-ri.eu/event/607/</a>
</span><span lang="EN-GB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-GB" style="color:black"><o:p> </o:p></span></p>
<p class="MsoPlainText"><b><span lang="EN-GB">Date:</span></b><span lang="EN-GB"> Thursday, May 4, 2017, 9:00-17:00
<o:p></o:p></span></p>
<p class="MsoPlainText"><b><span lang="EN-GB">Registration deadline:</span></b><span lang="EN-GB"> April 20, 2017<o:p></o:p></span></p>
<p class="MsoPlainText"><b><span lang="EN-GB">Lecturers:</span></b><span lang="EN-GB"> Dr. Fabio Baruffa, Dr. Luigi Iapichino (Intel Parallel Computing Centre @ LRZ)<o:p></o:p></span></p>
<p class="MsoPlainText"><b><span lang="EN-GB">Abstract:</span></b><span lang="EN-GB"> The workshop is organised as a compact course on techniques and methods, focused on code improvement and exploration of the latest Intel processor features, in particular
the vector units. During this optimisation process, the attendees will learn how to enable vectorisation using simple pragmas and more effective techniques, like changing data layout and alignment. This work is guided by the hints from the Intel compiler reports,
and using Intel Advisor. The outline of the workshop includes: basics on modern computer architectures, optimisation process and vectorisation, Intel Advisor. We provide also an N-body code, to support the described optimisation solutions with practical examples.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-GB" style="font-size:11.0pt;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Please also pass this course announcement to other interested colleagues.
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB" style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Information on further HPC courses:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"> - by LRZ: <a href="http://www.lrz.de/services/compute/courses/">http://www.lrz.de/services/compute/courses/</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"> - by the Gauss Centre of Supercomputing (GCS): <a href="http://www.gauss-centre.eu/training">http://www.gauss-centre.eu/training</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"> - by the PRACE Advanced Training Centres (PATCs):
<a href="http://www.training.prace-ri.eu/">http://www.training.prace-ri.eu/</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText">Kind regards,<o:p></o:p></p>
<p class="MsoPlainText">Volker Weinberg<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><span lang="EN-GB">--<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Dr. Volker Weinberg <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">PRACE Advanced Training Centre (PATC) Coordinator
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">email: <a href="mailto:weinberg@lrz.de">
weinberg@lrz.de</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-GB">address: Boltzmannstr. </span>1 - D-85748 Garching bei Muenchen
<o:p></o:p></p>
<p class="MsoPlainText">room: E.1.016<o:p></o:p></p>
<p class="MsoPlainText">phone: +49 (89) 35831-8863<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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