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<div class="WordSection1">
<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Dear HPC users of LRZ,<o:p></o:p></span></p>
<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">In the ever-growing complexity of computer architectures, code optimization has become the main route to keep pace with hardware advancements and effectively make use of current and upcoming
High Performance Computing systems.<br>
<br>
Have you ever asked yourself:<o:p></o:p></span></p>
<ul type="disc">
<li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l3 level1 lfo3">
Where does the performance of my application lay?<o:p></o:p></li><li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l3 level1 lfo3">
What is the maximum speed-up achievable on the architecture I am using?<o:p></o:p></li><li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l3 level1 lfo3">
Is my implementation matching the HPC objectives?<o:p></o:p></li></ul>
<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">In this PRACE workshop,
<strong><span style="font-family:"Calibri",sans-serif">two leading experts, from Intel and our Intel Parallel Computing Center team at LRZ</span></strong>, will answer these questions and provide a
<b>unique opportunity</b> to learn techniques, methods and solutions on how to improve code, how to enable new hardware features and how to use the roofline model to visualize the potential benefits of an optimization process.<br>
<br>
<strong><span style="font-family:"Calibri",sans-serif">Date</span></strong>: Thursday, 21 June - Friday, 22 June 2018, 9:00-17:00<br>
<strong><span style="font-family:"Calibri",sans-serif">Lecturers</span></strong>: Dr. Fabio Baruffa (Intel), Dr. Luigi Iapichino (Intel Parallel Computing Centre @ LRZ)<br>
<strong><span style="font-family:"Calibri",sans-serif">Further Details and Registration:</span></strong>
<a href="https://events.prace-ri.eu/event/727/">https://events.prace-ri.eu/event/727/</a><br>
<strong><span style="font-family:"Calibri",sans-serif">Registration deadline</span></strong>: 7 June 2018<br>
<br>
<strong><span style="font-family:"Calibri",sans-serif">Abstract</span></strong>: In this workshop we provide the opportunity to learn techniques, methods and solutions on how to improve code, how to enable the new hardware features and how to use the roofline
model to visualize the potential benefits of an optimization process. <br>
We will begin with a description of the latest micro-processor architectures and how the developers can efficiently use modern HPC hardware, in particular the vector units via SIMD programming and AVX-512 optimization and the memory hierarchy.<br>
The attendees are then conducted along the optimization process by means of hands-on exercises and learn how to enable vectorization using simple pragmas and more effective techniques, like changing data layout and alignment.<span style="color:black">
</span>The work is guided by the hints from the Intel compiler reports, and using Intel Advisor.<br>
We provide also an N-body code, to support the described optimization solutions with practical hands-on.<o:p></o:p></span></p>
<p><strong><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">A special focus will be dedicated to scalar and vector optimizations for the latest Intel Xeon Scalable processor, code-named Skylake, which is going to be utilized in the upcoming SuperMUC-NG
machine at LRZ.</span></strong><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p><strong><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">We will provide to the attendees access to Skylake processors and Intel tools using VM instances provided by Google Cloud Platform.</span></strong><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Please also pass this workshop announcement to other interested colleagues.<o:p></o:p></span></p>
<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Information on further HPC courses:<o:p></o:p></span></p>
<ul type="disc">
<li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l2 level1 lfo6">
by LRZ: <a href="http://www.lrz.de/services/compute/courses/">http://www.lrz.de/services/compute/courses/</a><o:p></o:p></li><li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l2 level1 lfo6">
by the Gauss Centre of Supercomputing (GCS): <a href="http://www.gauss-centre.eu/training">
http://www.gauss-centre.eu/training</a><o:p></o:p></li><li class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l2 level1 lfo6">
by German Centres (collected by the Gauß-Allianz): <a href="https://hpc-calendar.gauss-allianz.de/">
https://hpc-calendar.gauss-allianz.de/</a> <strong><span style="font-family:"Calibri",sans-serif">NEW!</span></strong><o:p></o:p></li><li class="MsoNormal" style="color:black;mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;mso-list:l2 level1 lfo6">
<span style="color:windowtext">by the Partnership for Advanced Computing in Europe (PRACE):
<a href="http://www.training.prace-ri.eu/">http://www.training.prace-ri.eu/</a></span><o:p></o:p></li></ul>
<p class="MsoPlainText">Kind regards,<o:p></o:p></p>
<p class="MsoPlainText">Volker Weinberg<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">--<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">Dr. Volker Weinberg
<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">- HPC Systems and Services -<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">email: <a href="mailto:weinberg@lrz.de">
weinberg@lrz.de</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">room: E.1.016<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">phone: +49 (89) 35831-8863<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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