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<p class="MsoPlainText">Dear HPC users of LRZ,<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">There are still places free for the "Intel Manycore Programming Workshop" at LRZ. We are happy to announce Dr.-Ing. Jan Eitzinger (RRZE) and Dr.-Ing. Michael Klemm (Intel, CEO of the OpenMP ARB) as invited speakers. The registration
deadline has been extended until Monday 9 July 2018.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><b>Date</b>: Monday, July 16, 2018 09:00 - Wednesday, July 18, 2018 16:00<o:p></o:p></p>
<p class="MsoPlainText"><b>Location</b>: LRZ, Garching b. München<o:p></o:p></p>
<p class="MsoPlainText"><b>Lecturers</b>: Dr. Momme Allalen, Dr. Luigi Iapichino, Dr. Volker Weinberg (LRZ), Dr.-Ing. Jan Eitzinger (RRZE), Dr.-Ing. Michael Klemm (Intel)<o:p></o:p></p>
<p class="MsoPlainText"><b>Registration</b>: <a href="https://events.prace-ri.eu/event/736/">
<span style="color:windowtext;text-decoration:none">https://events.prace-ri.eu/event/736/</span></a> <o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">The course discusses programming models and optimisation techniques for recent Intel processors in order to enable programmers to achieve good performance of their applications. The course will concentrate on techniques relevant for
the latest Intel Xeon Scalable processor, code-named Skylake, which is going to be utilized in the upcoming SuperMUC-NG machine at LRZ. Furthermore programming and optimisation techniques for Intel Knights Landing (KNL) based manycore systems like the KNL
cluster CoolMUC-3 at LRZ will be discussed.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Topics covered will include:<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">- Overview of the Intel Skylake and Intel MIC architecture<o:p></o:p></p>
<p class="MsoPlainText">- Overview of programming models<o:p></o:p></p>
<p class="MsoPlainText">- Vectorisation and basic performance optimisation<o:p></o:p></p>
<p class="MsoPlainText">- Code optimisation process for Intel processors<o:p></o:p></p>
<p class="MsoPlainText">- Intel profiling tools and roofline model<o:p></o:p></p>
<p class="MsoPlainText">- KNL memory modes and cluster modes, MCDRAM<o:p></o:p></p>
<p class="MsoPlainText">- Advanced optimisation techniques (RRZE)<o:p></o:p></p>
<p class="MsoPlainText">- Skylake programming using Intrinsics and Assembler (RRZE)<o:p></o:p></p>
<p class="MsoPlainText">- Skylake nodelevel- and microarchitecture in detail (Intel)<o:p></o:p></p>
<p class="MsoPlainText">- OpenMP SIMD (Intel)<o:p></o:p></p>
<p class="MsoPlainText">- OpenMP affinity and outlook on OpenMP 5.0 memory features (Intel)<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">The workshop will include both theoretical and practical hands-on sessions.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Kind regards,<o:p></o:p></p>
<p class="MsoPlainText">Volker Weinberg<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">--<o:p></o:p></p>
<p class="MsoPlainText">Dr. Volker Weinberg <o:p></o:p></p>
<p class="MsoPlainText">Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities<o:p></o:p></p>
<p class="MsoPlainText">- HPC Systems and Services -<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">email: <a href="mailto:weinberg@lrz.de"><span style="color:windowtext;text-decoration:none">weinberg@lrz.de</span></a><o:p></o:p></p>
<p class="MsoPlainText">address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
<o:p></o:p></p>
<p class="MsoPlainText">room: E.1.016<o:p></o:p></p>
<p class="MsoPlainText">phone: +49 (89) 35831-8863<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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