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<p class="MsoPlainText">Dear HPC users of LRZ,<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">There are still free places for the following upcoming PRACE courses at LRZ:<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><b>PRACE Course: Advanced Topics in High Performance Computing<o:p></o:p></b></p>
<p class="MsoPlainText"><b>Date:</b> Monday, March 18 - Thursday, March 21, 2019, 9:00-17:00<br>
<b>Location</b>: LRZ<br>
<b>Registration deadline extended until <span class="datetime">10 Mar 2019!</span><o:p></o:p></b></p>
<p class="MsoPlainText"><b><span lang="DE">Lecturers:</span></b><span lang="DE"> R. Bader, S. Mendez, V. Weinberg (LRZ), J. Eitzinger (RRZE), Andrey Semin (Intel)<o:p></o:p></span></p>
<p class="MsoPlainText"><b>Topics:</b> Processor-specific optimization, parallel I/O with MPI IO, Tuning I/O on LRZ's HPC systems, I/O profiling: Darshan tool, scientific data libraries: HDF5, scalable I/O library: SIONlib, PGAS programming with coarray Fortran
and Unified Parallel C.<o:p></o:p></p>
<p class="MsoPlainText">We are happy to announce that during the course Andrey Semin (Intel) will give a
<b>special lecture about the Intel Xeon Scalable (Skylake) processor architecture.<span style="color:#1F497D">
</span></b>This lecture will be devoted to the Intel Xeon Scalable (codenamed Skylake) processor that powers the brand new LRZ supercomputer: SuperMUC-NG. The lecture will cover details about Skylake core microarchitecture and Xeon uncore design. Additionally,
the lecture will provide details about SuperMUC-NG compute node design and the fabric system architecture.<o:p></o:p></p>
<p class="MsoPlainText"><b><o:p> </o:p></b></p>
<p class="MsoPlainText"><b>Further information and registration: </b><a href="https://events.prace-ri.eu/event/822/">https://events.prace-ri.eu/event/822/<br>
</a><span class="MsoHyperlink"><span style="color:windowtext;text-decoration:none"><o:p></o:p></span></span></p>
<p class="MsoNormal" align="center" style="text-align:center"><a href="https://events.prace-ri.eu/event/822/"><span style="color:windowtext;text-decoration:none"><o:p></o:p></span></a></p>
<div class="MsoNormal" align="center" style="text-align:center"><span class="MsoHyperlink"><span style="color:windowtext;text-decoration:none"><a href="https://events.prace-ri.eu/event/822/"><span style="color:windowtext;text-decoration:none">
<hr size="2" width="100%" align="center">
</span></a></span></span></div>
<p class="MsoNormal" align="center" style="text-align:center"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><b>PRACE Workshop: HPC code optimisation workshop<o:p></o:p></b></p>
<p class="MsoPlainText"><b>Date:</b> Monday, May 20 - Wednesday, May 22, 2019, 9:00-17:00<br>
<b>Location</b>: LRZ<br>
<b>Lecturers: </b>Dr. Fabio Baruffa (Intel), Dr. Mathias Gerald (LRZ), Dr. Luigi Iapichino (LRZ)<o:p></o:p></p>
<p class="MsoPlainText">Have you ever asked yourself:<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l2 level1 lfo2">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><i>Where does the performance of my application lay?
</i><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l2 level1 lfo2">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><i>What is the maximum speed-up achievable on the architecture I am using?
</i><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l2 level1 lfo2">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><i>Is my implementation matching the HPC objectives?</i><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">In this workshop, we will answer these questions and provide a unique opportunity to learn techniques, methods and solutions on how to improve code, how to enable the new hardware features and how to use the roofline model to visualize
the potential benefits of an optimization process.<b> </b><o:p></o:p></p>
<p class="MsoPlainText"><b><o:p> </o:p></b></p>
<p class="MsoPlainText"><b>Further information and registration: </b><a href="https://events.prace-ri.eu/event/872/">https://events.prace-ri.eu/event/872/</a><a href="https://events.prace-ri.eu/event/822/"><br>
</a><o:p></o:p></p>
<div class="MsoNormal" align="center" style="text-align:center">
<hr size="2" width="100%" align="center">
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<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><b>PRACE Course: Deep Learning and GPU programming workshop<o:p></o:p></b></p>
<p class="MsoPlainText"><b>Date:</b> Monday, June 3 - Thursday, June 6, 2019, 9:00-17:00<br>
<b>Location</b>: LRZ<br>
<b>Lecturers:</b> Dr. Momme Allalen, Dr. Juan Durillo Barrionuevo, Dr. Yu Wang, Dr. Volker Weinberg (LRZ)<o:p></o:p></p>
<p class="MsoPlainText"><b>Summary:</b> This new 4-days PRACE workshop offered for the first time at LRZ combines lectures about fundamentals of Deep Learning for Multiple Data Types and Multi-GPUs with lectures about Accelerated Computing with CUDA C/C++ and
OpenACC.<o:p></o:p></p>
<p class="MsoPlainText">The workshop is co-organized by LRZ and NVIDIA <a href="http://www.nvidia.co.uk/dli">
Deep Learning Institute</a> (DLI) for the Partnership for Advanced Computing in Europe (PRACE).
<o:p></o:p></p>
<p class="MsoPlainText"><b><o:p> </o:p></b></p>
<p class="MsoPlainText"><b>Further information: </b><a href="https://events.prace-ri.eu/event/860/">https://events.prace-ri.eu/event/860/</a><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<div class="MsoNormal" align="center" style="text-align:center">
<hr size="2" width="100%" align="center">
</div>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">We also want to point your attention to the new Best Practice Guides published by the Partnership for Advanced Computing in Europe (PRACE) under the leadership of LRZ under
<a href="http://www.prace-ri.eu/best-practice-guides/">http://www.prace-ri.eu/best-practice-guides/</a><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>Deep Learning</b>, February 2019
<a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-Deep-Learning.pdf">PDF</a> ,
<a href="http://www.prace-ri.eu/best-practice-guide-deep-learning">HTML</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>Modern Interconnects</b> , February 2019
<a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-Modern-Interconnects.pdf">
PDF</a> , <a href="http://www.prace-ri.eu/best-practice-guide-modern-interconnects">
HTML</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>ARM64</b>, February 2019 <a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-ARM64.pdf">
PDF</a> , <a href="http://www.prace-ri.eu/best-practice-guide-arm64/">HTML</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>Parallel I/O</b>, February 2019
<a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-Parallel-IO.pdf">PDF</a> ,
<a href="http://www.prace-ri.eu/best-practice-guide-parallel-i-o/">HTML</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>AMD EPYC</b>, February 2019
<a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-AMD.pdf">PDF</a> , <a href="http://www.prace-ri.eu/best-practice-guide-amd-epyc">
HTML</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l1 level1 lfo4">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>Best Practice Guide – <b>HPC for Data Science on the Cray Urika,
</b>January 2019 <a href="http://www.prace-ri.eu/IMG/pdf/Best-Practice-Guide-Data-Science.pdf">
PDF</a> , <a href="http://www.prace-ri.eu/best-practice-guide-hpc-for-data-science-on-the-cray-urika/">
HTML</a><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Topics for these Best Practice Guides include: a short description of the processor architecture, optimal porting of applications (e.g., choice of numerical libraries and compiler options); architecture specific optimisation and scaling
techniques; optimal system environment (e.g., tuneable system parameters, job placement and optimised system libraries); debugging tools, performance analysis tools and programming environment.<o:p></o:p></p>
<div class="MsoNormal" align="center" style="text-align:center">
<hr size="2" width="100%" align="center">
</div>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><b>Information on further HPC courses:<o:p></o:p></b></p>
<p class="MsoPlainText"><b><o:p> </o:p></b></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo6">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>by LRZ: <a href="http://www.lrz.de/services/compute/courses/">
http://www.lrz.de/services/compute/courses/</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo6">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>by the Gauss Centre of Supercomputing (GCS): <a href="http://www.gauss-centre.eu/training">
http://www.gauss-centre.eu/training</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo6">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>by German Centres (collected by the Gauß-Allianz):
<a href="https://hpc-calendar.gauss-allianz.de/">https://hpc-calendar.gauss-allianz.de/</a><o:p></o:p></p>
<p class="MsoPlainText" style="margin-left:36.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo6">
<![if !supportLists]><span style="font-size:10.0pt;font-family:Symbol"><span style="mso-list:Ignore">·<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]>by the Partnership for Advanced Computing in Europe (PRACE):
<a href="http://www.training.prace-ri.eu/">http://www.training.prace-ri.eu/</a><o:p></o:p></p>
<p class="MsoPlainText"><br>
Please also pass this announcement to other interested colleagues.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Kind regards,<o:p></o:p></p>
<p class="MsoPlainText">Volker Weinberg<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">-- <o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">Dr. Volker Weinberg
<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">- HPC Systems and Services -<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">email: <a href="mailto:weinberg@lrz.de">
weinberg@lrz.de</a><o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">room: E.1.016<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB">phone: +49 (89) 35831-8863<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="mso-fareast-language:EN-GB"><o:p> </o:p></span></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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