Public Lectures on Intel Xeon Phi & OpenMP 4.0

Weinberg, Volker Volker.Weinberg at
Mo Mär 17 16:09:09 CET 2014

Dear HPC users of LRZ,

Currently, together with IBM, LRZ is configuring the new SuperMIC cluster for user operation in Q2 2014. SuperMIC consists of 32 Intel Xeon (Ivy Bridge) host nodes and 64 Intel Xeon Phi coprocessors based on Intel's Many Integrated Core (MIC) architecture.
Users interested in using the SuperMIC cluster and/or the new features of OpenMP 4.0 are invited to join the following public lectures given by Dr. M. Klemm, Intel.
The lectures are part of the course "Advanced Topics in High Performance Computing", but can be attended by interested users without registration.

Location: LRZ Building, Hörsaal, University campus Garching, near Munich (Boltzmannstr. 1 - D-85748 Garching bei Muenchen)

Date: Monday, March 31st, 2014, 9:00-12:00

Speaker: Dr. M. Klemm (Intel)


Lecture I: 09:00 - approx. 10:45: The Intel Xeon Phi Coprocessor Architecture and Programming

The Intel Xeon Phi Coprocessor is a massively parallel compute device that provides additional compute power for traditional compute servers. It is designed to retain the flexibility and programmability of Intel Architecture, while providing a large number of threads and extra-wide SIMD instructions. In this presentation, we will present the coprocessor architecture from a hardware and software perspective. We will discuss the tools and programming models available. While some of the well-known parallel programming models will be touched, the focus will be on the coprocessor-specific extensions of these programming models.

Lecture II: 11:00 - 12:00: OpenMP 4.0 for HPC in a Nutshell 

OpenMP 4.0 is the current release of the OpenMP API specification.  It added new major features to the OpenMP language to incorporate latest technological trends in HPC and beyond. The new features will significantly increase the expressiveness of OpenMP and its applicability for complex HPC codes. In this presentation, we will provide an in-depth overview of the new features.  The presented features include user-defined reductions, support for SIMD instructions, support for accelerators/coprocessors, and affinity.


Dr. Michael Klemm is part of Intel's Software and Services Group, Developer Relations Division. His focus is on High Performance and Throughput Computing. Michael received a Doctor of Engineering degree (Dr.-Ing.) in Computer Science from the Friedrich-Alexander-University Erlangen-Nuremberg, Germany.  His research focus was on compilers and runtime optimizations for distributed systems. Michael's areas of interest include compiler construction, design of programming languages, parallel programming, and performance analysis and tuning. Michael is Intel representative in the OpenMP Language Committee and leads the efforts to develop error handling features for OpenMP.

Please also pass this lecture announcement to interested colleagues.

Kind regards,
Volker Weinberg

Dr. Volker Weinberg                     
Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften
- High Performance Computing Group -

email:   weinberg at
address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen             
room:    E.1.016
phone:   +49 (89) 35831-8863

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