Intel MIC Programming Workshop @ IT4Innovations
Volker.Weinberg at lrz.de
Mi Jan 25 12:47:24 CET 2017
Dear HPC users,
we are pleased to announce that LRZ will offer a 2-day PRACE Advanced Training Centre (PATC) workshop on February 7-8, 2017 at IT4Innovations, Ostrava, Czech Republic, completely devoted to Intel Xeon Phi programming. The course discusses Intel's Many Integrated Core (MIC) architecture in detail and covers various programming and optimisation techniques for Intel Xeon Phi coprocessors. There are still places free!
The topics of the first 1.5 days reach from an introduction about the Intel MIC architecture and various Intel Xeon Phi programming models (Offloading, Native mode, MKL, OpenMP, MPI etc.) to advanced topics about vectorisation and performance optimisation, interleaved with many hands-on sessions on the Intel Xeon Phi based Salomon system at IT4Innovations.
During a plenum session on the last day invited speakers talk about MIC experience and best practice recommendations using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations. Talks presented include topics like Acceleration of the ESPRESO domain decomposition library, Acceleration of Blender Cycles Render Engine using Intel Xeon Phi, Boundary element quadrature schemes for multi- and many-core architectures, Exploring the impact of Intel MIC and Intel CPU architectures on accelerating scientific applications and Acceleration of the k-Wave toolbox on Xeon Phi.
For details and registration see:
The registration deadline has been extended to 1.2.2017.
The workshop is collocated with a scientific workshop organised within the joint German-Czech project CzeBaCCA on "HPC in Atmosphere Modelling and Air Related Environmental Hazards" taking place at IT4Innovations immediately after the MIC Programming Workshop.
See http://prace.it4i.cz/en/high-performance-computing-in-atmosphere-modelling-and-air-related-environmental-hazards for details.
Please also pass this course announcement to other interested colleagues.
Information on further HPC courses:
- by LRZ: http://www.lrz.de/services/compute/courses/
- by the Gauss Centre of Supercomputing (GCS): http://www.gauss-centre.eu/training
- by the PRACE Advanced Training Centres (PATCs): http://www.training.prace-ri.eu/
Dr. Volker Weinberg
PRACE Advanced Training Centre (PATC) Coordinator
Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften
email: mailto:weinberg at lrz.de
address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
phone: +49 (89) 35831-8863
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