Intel MIC Programming Workshop @ LRZ, Germany

[Weinberg, Volker]

Dear HPC users,



we are pleased to announce that LRZ will offer a 3-day PRACE Advanced Training Centre (PATC) workshop "Intel MIC Programming Workshop" on June 26-28, 2017 at LRZ, Germany, completely devoted to Intel Xeon Phi programming.



The workshop discusses Intel's Many Integrated Core (MIC) architecture and programming models for Intel Xeon Phi co-/processors in order to enable programmers to achieve good performance of their applications. The workshop will mainly concentrate on techniques relevant for Knights Landing (KNL) based systems, like the future KNL cluster CoolMUC3 to be installed at LRZ, soon.



The workshop covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-/processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications.



There will also be a session with invited talks by speakers from Intel, IPCC at LRZ, IPCC at TUM, IPCC at IT4Innovations, IPP, RRZE and the University of Regensburg about Intel Xeon Phi - especially KNL - experience and best practice recommendations.



For details and registration see:



https://events.prace-ri.eu/event/609/



The course is developed within the joint German-Czech Republic project CzeBaCCA. A workshop on "HPC for natural hazard assessment and disaster mitigation" of this project will take place at LRZ directly after this course (see https://www.lrz.de/services/compute/courses/2017-06-28_hnha1s17/ ).



Please also pass this course announcement to other interested colleagues.



Information on further HPC courses:



  - by LRZ:  http://www.lrz.de/services/compute/courses/

  - by the Gauss Centre of Supercomputing (GCS):   http://www.gauss-centre.eu/training

  - by the PRACE Advanced Training Centres (PATCs): http://www.training.prace-ri.eu/





Kind regards,

Volker Weinberg



--

Dr. Volker Weinberg

PRACE Advanced Training Centre (PATC) Coordinator

Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften



email:   weinberg at lrz.de<mailto:weinberg at lrz.de>

address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen

room:    E.1.016

phone:   +49 (89) 35831-8863


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