Dear HPC users, Interested in optimising your parallel code? Then join our new one-day PRACE “HPC Code Optimisation Workshop” in May at Leibniz Supercomputing Centre, Germany. Two leading experts from our Intel Parallel Computing Centre will share their know-how in code optimisation. NEW PRACE Workshop @ LRZ: HPC Code Optimisation Workshop https://events.prace-ri.eu/event/607/ Date: Thursday, May 4, 2017, 9:00-17:00 Registration deadline: April 20, 2017 Lecturers: Dr. Fabio Baruffa, Dr. Luigi Iapichino (Intel Parallel Computing Centre @ LRZ) Abstract: The workshop is organised as a compact course on techniques and methods, focused on code improvement and exploration of the latest Intel processor features, in particular the vector units. During this optimisation process, the attendees will learn how to enable vectorisation using simple pragmas and more effective techniques, like changing data layout and alignment. This work is guided by the hints from the Intel compiler reports, and using Intel Advisor. The outline of the workshop includes: basics on modern computer architectures, optimisation process and vectorisation, Intel Advisor. We provide also an N-body code, to support the described optimisation solutions with practical examples. Please also pass this course announcement to other interested colleagues. Information on further HPC courses: - by LRZ: http://www.lrz.de/services/compute/courses/ - by the Gauss Centre of Supercomputing (GCS): http://www.gauss-centre.eu/training - by the PRACE Advanced Training Centres (PATCs): http://www.training.prace-ri.eu/ Kind regards, Volker Weinberg -- Dr. Volker Weinberg PRACE Advanced Training Centre (PATC) Coordinator Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities email: weinberg@lrz.de<mailto:weinberg@lrz.de> address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen room: E.1.016 phone: +49 (89) 35831-8863