Dear HPC users of LRZ, we are pleased to announce that LRZ will offer a 3-day PRACE Advanced Training Centre (PATC) workshop on June 27-29, 2016 completely devoted to Intel Xeon Phi programming. The course discusses Intel's Many Integrated Core (MIC) architecture in detail and covers various programming and optimisation techniques for Intel Xeon Phi coprocessors. The first 2 days provide an introduction about the Intel MIC architecture and various Intel Xeon Phi programming models, interleaved with many hands-on sessions on the Intel Xeon Phi based SuperMIC system at LRZ. The last day presents advanced topics about performance optimisation and Intel's new Knights Landing (KNL) architecture. During a plenum session invited speakers from Intel, RRZE, IPP, IT4Innovations, IPCC@TUM and IPCC@LRZ talk about MIC experience and best practice recommendations using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations (Czech Republic), the largest Intel Xeon Phi based system in Europe. For details and registration see: https://www.lrz.de/services/compute/courses/2016-06-27_hphi1s16/ The workshop is collocated with a three-day scientific workshop on "High Performance Computing for Water Related Hazards" taking place at LRZ on June 29 - July 1, 2016. See https://www.lrz.de/services/compute/courses/2016-06-29_hwrh1s16/ Please also pass this course announcement to other interested colleagues. Information on further HPC courses: - by LRZ: http://www.lrz.de/services/compute/courses/ - by the Gauss Centre of Supercomputing (GCS): http://www.gauss-centre.eu/training - by the PRACE Advanced Training Centres (PATCs): http://www.training.prace-ri.eu/ Kind regards, Volker Weinberg -- Dr. Volker Weinberg PRACE Advanced Training Centre (PATC) Coordinator Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften email: mailto:weinberg@lrz.de address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen room: E.1.016 phone: +49 (89) 35831-8863