Sehr geehrte Damen und Herren, hiermit moechten wir Sie zu folgendem Vortrag am 14.11.2013 im Hoersaal des LRZ einladen: Titel: Architecture Simulation for HPC Developers Referent: Josef Weidendorfer Beginn: 14.11.2013 15:15 Uhr Dauer: 45 min Inhalt: Simulation of models for computer system (or components thereof) traditionally is used in the design and evaluation of new hardware configurations and enhancements. However, architecture simulation also can be used for performance analysis and verification of effects of code modifications. While it can not replace measurement on real hardware, it complements conventional measurement methods with attractive benefits such as reproducability, non-existing measurement overhead, and advanced performance metrics. In this talk, simulation of the memory hierarchy will be shown to be a good candidate for architecture simulation that can help developers to identify performance bottlenecks, ways to reduce them, and check the effect of modifications. Starting from simple cache simulation providing hit/miss counts (as available with Cachegrind/Callgrind on SuperMUC), we show more detailed analysis methods (e.g. on memory access locality, bandwidth requirements) which can be done by starting your program binary under supervision of a simulator tool. Naehere Informationen (auch zu den anderen Vortraegen im Rahmen der Vortragsreihe) unter http://www.lrz.de/services/termine/vr-it-betrieb/ wise_13_14 Diese Information finden Sie im WWW unter http://www.lrz-muenchen.de/services/schulung/aktuell/ali4703/ Ilya Saverchenko