PRACE PATC Course: Introduction to SuperMUC

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Do Jun 27 10:43:25 CEST 2013

    Date:     July 8-11, 2013 10:00 - 17:00                            
   Location:   LRZ Building, University campus Garching, near Munich    
               (Lecture room H.E.009)                                   
               This four-day workshop gives an introduction to the usage
               of the new Petaflop class Supercomputer at LRZ, SuperMUC.
               The first three days of this are dedicated to            
               presentations by Intel on their software development     
               stack (compilers, tools and libraries); the remaining day
               will be comprised of talks and exercises delivered by IBM
               and LRZ on usage of the IBM-specific aspects of the new  
               system (IBM MPI, LoadLeveler, HPC Toolkit) and           
               recommendations on tuning and optimizing for the new     
               The following schedule is preliminary and may undergo    
               Monday schedule:                                         
                 * Introduction to the x86 Westmere and Sandy Bridge    
                   Processor Architecture                               
                 * Usage of Intel Compilers: switches, optimization,    
                   profiling, OpenMP, advanced features                 
                 * Usage of the Intel debugger                          
                 * Explicit and compiler-directed vectorization with SSE
                   and AVX                                              
               Tuesday schedule:                                        
   Contents:     * Programming for NUMA                                 
                 * Intel Cilk Plus                                      
                 * Fortran standard support and extensions in Intel     
                 * Intel Inspector XE (correctness checking for memory  
                   and threading)                                       
                 * Threading Building Blocks, OpenCL and other parallel 
                   programming models                                   
                 * Static Security Analysis                             
                 * Performance Libraries (MKL, IPP)                     
                 * VTune Amplifier XE (performance analysis)            
               Wednesday schedule:                                      
                 * Intel Performance Monitoring Unit (PMU) and other    
                   performance analysis tools                           
                 * Intel Cluster Tools Overview and Usage               
                 * Intel Many Integrated Core (MIC) Architecture        
                 * A case study illustrating the use of the Intel       
               Thursday schedule:                                       
                 * Using LoadLeveler for batch queuing                  
                 * IBM's parallel environment                           
                 * Performance Tools (High Performance Toolkit, Eclipse 
                   User Interface) including a demonstration.           
               Participants should have good knowledge of HPC-related   
 Prerequisites programming, in particular MPI, OpenMP and at least one  
               of the languages C, C++ or Fortran.                      
   Language:   English                                                  
   Teachers:   Heinz Bast, Georg Zitzlsberger (Intel), Achim Boemelburg,
               Florian Merz, Christoph Pospiech (IBM), LRZ staff        
               Please register via the LRZ registration form: http://   
               (select course HMUC1S13)                                 

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 Matthias Brehm

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