PRACE PATC Course: Introduction to SuperMUC- the 3 Petaflop Supercomputer at LRZ

LRZ aktuell publish at lrz.de
Do Jun 27 12:09:10 CEST 2013


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 |    Date:    |July 8-11, 2013 10:00 - 17:00                          |
 |-------------+-------------------------------------------------------|
 |  Location:  |LRZ Building, University campus Garching, near Munich  |
 |             |(Lecture room H.E.009)                                 |
 |-------------+-------------------------------------------------------|
 |             |This four-day workshop gives an introduction to the    |
 |             |usage of the new Petaflop class Supercomputer at LRZ,  |
 |             |SuperMUC. The first three days of this are dedicated to|
 |             |presentations by Intel on their software development   |
 |             |stack (compilers, tools and libraries); the remaining  |
 |             |day will be comprised of talks and exercises delivered |
 |             |by IBM and LRZ on usage of the IBM-specific aspects of |
 |             |the new system (IBM MPI, LoadLeveler, HPC Toolkit) and |
 |             |recommendations on tuning and optimizing for the new   |
 |             |system.                                                |
 |             |                                                       |
 |             |The following schedule is preliminary and may undergo  |
 |             |changes.                                               |
 |             |                                                       |
 |             |Monday schedule:                                       |
 |             |                                                       |
 |             |  * Introduction to the x86 Westmere and Sandy Bridge  |
 |             |    Processor Architecture                             |
 |             |  * Usage of Intel Compilers: switches, optimization,  |
 |             |    profiling, OpenMP, advanced features               |
 |             |  * Usage of the Intel debugger                        |
 |             |  * Explicit and compiler-directed vectorization with  |
 |             |    SSE and AVX                                        |
 |             |                                                       |
 |             |Tuesday schedule:                                      |
 |             |                                                       |
 |  Contents:  |  * Programming for NUMA                               |
 |             |  * Intel Cilk Plus                                    |
 |             |  * Fortran standard support and extensions in Intel   |
 |             |    Fortran                                            |
 |             |  * Intel Inspector XE (correctness checking for memory|
 |             |    and threading)                                     |
 |             |  * Threading Building Blocks, OpenCL and other        |
 |             |    parallel programming models                        |
 |             |  * Static Security Analysis                           |
 |             |  * Performance Libraries (MKL, IPP)                   |
 |             |  * VTune Amplifier XE (performance analysis)          |
 |             |                                                       |
 |             |Wednesday schedule:                                    |
 |             |                                                       |
 |             |  * Intel Performance Monitoring Unit (PMU) and other  |
 |             |    performance analysis tools                         |
 |             |  * Intel Cluster Tools Overview and Usage             |
 |             |  * Intel Many Integrated Core (MIC) Architecture      |
 |             |  * A case study illustrating the use of the Intel     |
 |             |    toolchain                                          |
 |             |                                                       |
 |             |Thursday schedule:                                     |
 |             |                                                       |
 |             |  * Using LoadLeveler for batch queuing                |
 |             |  * IBM's parallel environment                         |
 |             |  * Performance Tools (High Performance Toolkit,       |
 |             |    Eclipse User Interface) including a demonstration. |
 |-------------+-------------------------------------------------------|
 |             |Participants should have good knowledge of HPC-related |
 |Prerequisites|programming, in particular MPI, OpenMP and at least one|
 |             |of the languages C, C++ or Fortran.                    |
 |-------------+-------------------------------------------------------|
 |  Language:  |English                                                |
 |-------------+-------------------------------------------------------|
 |             |Heinz Bast, Georg Zitzlsberger (Intel), Achim          |
 |  Teachers:  |Boemelburg, Florian Merz, Christoph Pospiech (IBM), LRZ|
 |             |staff                                                  |
 |-------------+-------------------------------------------------------|
 |             |Please register via the LRZ registration form: http:// |
 |Registration:|www.lrz-muenchen.de/services/schulung/kursanmeldung    |
 |             |(select course HMUC1S13)                               |
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 Diese Information finden Sie im WWW unter
 http://www.lrz-muenchen.de/services/compute/aktuell/ali4612/

 Matthias Brehm



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