NEW PRACE Workshop: HPC code optimization workshop
Volker.Weinberg at lrz.de
Mi Apr 25 12:42:11 CEST 2018
Dear HPC users of LRZ,
In the ever-growing complexity of computer architectures, code optimization has become the main route to keep pace with hardware advancements and effectively make use of current and upcoming High Performance Computing systems.
Have you ever asked yourself:
* Where does the performance of my application lay?
* What is the maximum speed-up achievable on the architecture I am using?
* Is my implementation matching the HPC objectives?
In this PRACE workshop, two leading experts, from Intel and our Intel Parallel Computing Center team at LRZ, will answer these questions and provide a unique opportunity to learn techniques, methods and solutions on how to improve code, how to enable new hardware features and how to use the roofline model to visualize the potential benefits of an optimization process.
Date: Thursday, 21 June - Friday, 22 June 2018, 9:00-17:00
Lecturers: Dr. Fabio Baruffa (Intel), Dr. Luigi Iapichino (Intel Parallel Computing Centre @ LRZ)
Further Details and Registration: https://events.prace-ri.eu/event/727/
Registration deadline: 7 June 2018
Abstract: In this workshop we provide the opportunity to learn techniques, methods and solutions on how to improve code, how to enable the new hardware features and how to use the roofline model to visualize the potential benefits of an optimization process.
We will begin with a description of the latest micro-processor architectures and how the developers can efficiently use modern HPC hardware, in particular the vector units via SIMD programming and AVX-512 optimization and the memory hierarchy.
The attendees are then conducted along the optimization process by means of hands-on exercises and learn how to enable vectorization using simple pragmas and more effective techniques, like changing data layout and alignment. The work is guided by the hints from the Intel compiler reports, and using Intel Advisor.
We provide also an N-body code, to support the described optimization solutions with practical hands-on.
A special focus will be dedicated to scalar and vector optimizations for the latest Intel Xeon Scalable processor, code-named Skylake, which is going to be utilized in the upcoming SuperMUC-NG machine at LRZ.
We will provide to the attendees access to Skylake processors and Intel tools using VM instances provided by Google Cloud Platform.
Please also pass this workshop announcement to other interested colleagues.
Information on further HPC courses:
* by LRZ: http://www.lrz.de/services/compute/courses/
* by the Gauss Centre of Supercomputing (GCS): http://www.gauss-centre.eu/training
* by German Centres (collected by the Gauß-Allianz): https://hpc-calendar.gauss-allianz.de/ NEW!
* by the Partnership for Advanced Computing in Europe (PRACE): http://www.training.prace-ri.eu/
Dr. Volker Weinberg
Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities
- HPC Systems and Services -
email: weinberg at lrz.de<mailto:weinberg at lrz.de>
address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
phone: +49 (89) 35831-8863
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