Online Courses by LRZ in June

Weinberg, Volker Volker.Weinberg at
Fr Mai 29 09:39:08 CEST 2020

Dear users of LRZ,

we are happy to announce that we have further extended our online training programme in June. There are still some places available!

Please mind that registration is necessary since the details to access the online courses will be provided to the registered attendees only.

PRACE Workshop: HPC code optimisation workshop

Date: Monday, June 8 - Wednesday, June 10, 2020, 10:00-16:00 CEST
Registration Deadline: June 3, 2020 (extended!)
Lecturers: Momme Allalen (LRZ), Fabio Baruffa (Intel), Gennady Fedorov (Intel), Mathias Gerald (LRZ),  Thomas Gruber (RRZE), Carla Guillen (LRZ), Michael Steyer (Intel), Igor Vorobtsov (Intel), Volker Weinberg (LRZ)

We will begin with a description of the latest micro-processor architectures and how the developers can efficiently use modern HPC hardware, in particular the vector units via SIMD programming and AVX-512 optimization and the memory hierarchy. The attendees are then conducted along the optimization process by means of hands-on exercises and learn how to enable vectorization using simple pragmas and more effective techniques, like changing data layout and alignment. The work is guided by the hints from the Intel® compiler reports, and using Intel® Advisor. Besides Intel® Advisor, the participants will also be guided to the use of Intel® VTune(tm) Amplifier, Intel® Application Performance Snapshot and LIKWID as tools for investigating and improving the performance of a HPC application. We further cover the Intel® Math Kernel Library (MKL), in order to show how to gain performance through the use of libraries. The workshop is a PRACE training event organized by LRZ in cooperation with Intel and RRZE.

PRACE Workshop: Deep Learning and GPU programming workshop

Date: Monday, June 15 - Thursday, June 18, 2020, 10:00-16:00 CEST
Registration Deadline: June 8, 2020 (extended!)
Lecturers: Dr. Momme Allalen, Dr. Juan Durillo Barrionuevo, Dr. Volker Weinberg (LRZ and NVIDIA University Ambassadors), Georg Zitzlsberger (IT4Innovations and NVIDIA University Ambassador)

Learn how to train and deploy a neural network to solve real-world problems, how to generate effective descriptions of content within images and video clips, how to effectively parallelize training of deep neural networks on Multi-GPUs and how to accelerate your applications with CUDA C/C++ and OpenACC. This 4-days workshop  combines lectures about fundamentals of Deep Learning for Multiple Data Types and Multi-GPUs with lectures about Accelerated Computing with CUDA C/C++ and OpenACC. The lectures are interleaved with many hands-on sessions using Jupyter Notebooks. The exercises will be done on a fully configured GPU-accelerated workstation in the cloud. The workshop is co-organized by LRZ, IT4Innovations and NVIDIA Deep Learning Institute (DLI) for the Partnership for Advanced Computing in Europe (PRACE).

PRACE Course: Introduction to hybrid programming in HPC

Date: Wednesday, June 17 08:45 - Friday, June 19, 2020 16:00 CEST
Registration Deadline: June 2, 2020
Lecturers: Dr. habil. Georg Hager (RRZE, Uni. Erlangen), Dr. Rolf Rabenseifner (HLRS, Uni. Stuttgart), Dr. Claudia Blaas-Schenner, Dr. Irene Reichl (VSC Research Center, TU Wien)

Most HPC systems are clusters of shared memory nodes. To use such systems efficiently both memory consumption and communication time has to be optimized. Therefore, hybrid programming may combine the distributed memory parallelization on the node interconnect (e.g., with MPI) with the shared memory parallelization inside of each node (e.g., with OpenMP or MPI-3.0 shared memory). This course analyses the strengths and weaknesses of several parallel programming models on clusters of SMP nodes. LRZ has joined forces with VSC Vienna and HLRS Stuttgart and will offer this course online as a replacement for the course originally scheduled in April at LRZ.

Intel OneAPI for FPGAs

Date: Friday, June 19, 2020, 13:00-19:00 CEST
Registration Deadline: June 5, 2020
Lecturer: Susannah Martin (Intel)

In this course you will learn to use the Intel® oneAPI Base Toolkit and the Intel® FPGA Add-On for oneAPI Base Toolkit to target an FPGA. We will explore how your Data Parallel C++ (DPC++) source code becomes a custom compute unit, and what resources are utilized in the FPGA to build it. The proper development flow for working with an FPGA will be presented: emulation, interpreting optimization reports, and performance analysis on the FPGA. Finally, you will be introduced to important optimization concepts such as pipelining loop iterations and architecting kernel memory. The course includes lectures, demonstrations and hands-on sessions and is offered by Intel in cooperation with LRZ.

Optimizing OpenCL Programs for Intel FPGAs

Date: Thursday, June 25, 2020, 09:00-18:00 CEST
Registration Deadline: June 15, 2020
Lecturer: Marlon Price (Intel)

The course covers various optimization techniques to implement high performance OpenCL(tm) applications on FPGAs. We'll use various debug & analysis tools available in the Intel® FPGA SDK for OpenCL(tm) software technology to boost performance of OpenCL kernels. The first half of the lecture focuses on the optimization of single work-item kernels & the utilization of channel constructs & OpenCL kernel pipes. The second half of the lecture focuses on the optimization of NDRange kernels & the effective utilization of FPGA memory resources. Throughout the lecture we will discuss good coding practices for FPGAs & tool features to improve OpenCL kernel performance on FPGAs. The course is offered by Intel in cooperation with LRZ.

Information on further HPC courses:

  *   by LRZ:
  *   by the Gauss Centre of Supercomputing (GCS):
  *   by German Centres (collected by the Gauß-Allianz):
  *   by the Partnership for Advanced Computing in Europe (PRACE):
We are looking forward to meeting you online!

Kind regards,
Volker Weinberg

Dr. Volker Weinberg
HPC Training and Education Coordinator
Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities

email:   weinberg at<mailto:weinberg at>
address: Boltzmannstr. 1 - D-85748 Garching bei Muenchen
room:    E.1.016
phone:   +49 (89) 35831-8863

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